Exploiting multi-megabyte on-chip memory hierarchies

Funding Details
Natural Sciences and Engineering Research Council of Canada
  • Grant type: Collaborative Research and Development Grants
  • Years: 2010/11 to 2012/13
  • Total Funding: $119,970
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Project Summary

At the core of virtually all modern electronic devices such as computers, cell phones, mp3 players, game consoles, and network routers there is at least one processor. A processor is a device that can manipulate information represented as numbers. Processors are extremely useful because they can interact with the environment via sensors (e.g., a microphone) and actuators (e.g., a speaker). Processors are also extremely useful in scientific exploration as they can be used to evaluate complex models of physical phenomena such as chemical, biological and inter-planetary interactions that too expensive or impractical to study otherwise. Today many everyday activities and much of scientific exploration rely on the availability of optimized, inexpensive processors. Historically, it was possible to continuously improve the performance and other characteristics of processors (e.g., energy consumption) while reducing cost. A typical computer today costs at least 10 times less and is about 1000 times more powerful than a computer of the early 80s. Much of the communications and computing industry relies on this trend. A key mechanism for improving processors is computer architecture, which studies how to build processors given the available manufacturing technologies while taking into consideration the target application(s). Computer architecture faces continuous challenges because the properties of the underlying technology and the target applications change significantly over time. This research is targeted at improving processors by addressing new challenges and taking advantage of new opportunities that stem from the continuous shrinking of the underlying manufacturing technology and from the emergence of multimedia and internet oriented uses. The challenges addressed include performance, design complexity, and energy consumption. This work targets the design of a on-chip memory hierarchies proposing coarse-grain management and tracking, and leveraging its capacity to better anticipate and optimize for application needs. It is primarily high-end performance-oriented processors used in large data centers (such as those used for internet-based services and in large organizations) that will benefit from this work.

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